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Modeling of the MOSFET inversion charge and drain current in moderate inversionALTSCHUL, V; SHACHAM-DIAMAND, Y.I.E.E.E. transactions on electron devices. 1990, Vol 37, Num 8, pp 1909-1915, issn 0018-9383, 7 p.Article

Effect of amorphization on activation and deactivation of boron in source/drain, channel and polygatePAWLAK, B. J; DUFFY, R; CAMILLO-CASTILLO, R. A et al.Proceedings - Electrochemical Society. 2005, pp 43-49, issn 0161-6374, isbn 1-56677-463-2, 7 p.Conference Paper

Analytical low-frequency 1/f noise model for lightly-doped-drain mosfets operating in the linear regionSHENG-LYANG JANG.Solid-state electronics. 1993, Vol 36, Num 6, pp 899-903, issn 0038-1101Article

A new MOSFET with large-tilt-angle implanted drain (LATID) structureHORI, T; KURIMOTO, K.IEEE electron device letters. 1988, Vol 9, Num 6, pp 300-302, issn 0741-3106Article

Pt-germanide schottky source/drain germanium p-MOSFET with HfO2 gate dielectric and TaN gate electrodeRUI LI; LEE, S. J; YAO, H. B et al.IEEE electron device letters. 2006, Vol 27, Num 6, pp 476-478, issn 0741-3106, 3 p.Article

Cost effective implementation of a 90 V RESURF P-type drain extended MOS in a 0.35 μm based smart power technologyBAKEROOT, B; VERMANDEL, M; DOUTRELOIGNE, J et al.ESSCIRC 2002 : European solid-state circuits conferenceEuropean solid-state device research conference. 2002, pp 291-294, isbn 88-900847-8-2, 4 p.Conference Paper

Low temperature polycrystalline silicon thin film transistorsJIN JANG; JAI II RYU; SOO YOUNG YOON et al.Vacuum. 1998, Vol 51, Num 4, pp 769-775, issn 0042-207XArticle

Theory of the drain leakage current in silicon MOSFETsTANAKA, S.Solid-state electronics. 1995, Vol 38, Num 3, pp 683-691, issn 0038-1101Article

Temperature dependence of gate induced drain leakage current in silicon CMOS devicesRAIS, K; BALESTRA, F; GHIBAUDO, G et al.Electronics Letters. 1994, Vol 30, Num 1, pp 32-34, issn 0013-5194Article

A new drain engineering structure-SCD-LDD (surface counter doped LDD) for improved hot carrier reliabilityJIH WEN CHOU; CHUN YUN CHANG; LIEN TSE HO et al.Japanese journal of applied physics. 1993, Vol 32, Num 9A, pp L1203-L1205, issn 0021-4922, 2Article

Characteristics of field-induced-drain (FID) poly-Si TFT's with high ON/OFF current ratioTANAKA, K; NAKAZAWA, K; SUYAMA, S et al.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 4, pp 916-920, issn 0018-9383Article

Design for suppression of gate-induced drain leakage in LDD MOSFET's using a quasi-two-dimensional analytical modelPARKE, S. A; MOON, J. E; WANN, H.-J. C et al.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 7, pp 1694-1703, issn 0018-9383Article

Ageing of metal-semiconductor field effect transistorsCHATTOPADHYAY, P.Journal of physics. D, Applied physics (Print). 1998, Vol 31, Num 9, pp 1060-1063, issn 0022-3727Article

A new approach for modeling the MOSFET using a simple, continuous analytical expression for drain conductance which includes velocity-saturation in a fundamental wayBANDY, W. R; WINTON, R. S.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 5, pp 475-483, issn 0278-0070Article

P-MOSFET's with ultra-shallow solid-phase-diffused drain structured produced by diffusion from BSG gate-sidewallSAITO, M; YOSHITOMI, T; IWAI, H et al.I.E.E.E. transactions on electron devices. 1993, Vol 40, Num 12, pp 2264-2272, issn 0018-9383Article

MISNAN : a physically based continuous MOSFET model for CAD applicationsBOOTHROYD, A. R; TARASEWICZ, S. W; SLABY, C et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 12, pp 1512-1529, issn 0278-0070Article

Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devicesJAMAL DEEN, M; YAN, Z. X.I.E.E.E. transactions on electron devices. 1990, Vol 37, Num 7, pp 1707-1713, issn 0018-9383, 7 p.Article

Polymer gate dielectrics with self-assembled monolayers for high-mobility organic thin-film transistors based on copper phthalocyanineYANMING SUN; YUNQI LIU; YING WANG et al.Applied physics. A, Materials science & processing (Print). 2009, Vol 95, Num 3, pp 777-780, issn 0947-8396, 4 p.Article

A new LDD structure : total overlap with polysilicon spacer (TOPS)MOON, J. E; GARFINKEL, T; CHUNG, J et al.IEEE electron device letters. 1990, Vol 11, Num 5, pp 221-223, issn 0741-3106, 3 p.Article

An analytical model for the internal electric field in submicrometer MOSFET'sDEJENFELT, A. T.I.E.E.E. transactions on electron devices. 1990, Vol 37, Num 5, pp 1352-1363, issn 0018-9383, 12 p., 0Article

Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulationHU, M.-C; JANG, S.-L.International journal of electronics. 1998, Vol 84, Num 3, pp 167-185, issn 0020-7217Article

A 0.30 μm buried channel PMOS FET with surface-pocket drain structureGOTO, Y; GOTO, F; HOMMA, A et al.NEC research & development. 1994, Vol 35, Num 2, pp 149-155, issn 0547-051XArticle

Model for the anomalous off-current of polysilicon thin-film transistors and diodesRODRIGUEZ, A; MORENO, E. G; PATTYN, H et al.I.E.E.E. transactions on electron devices. 1993, Vol 40, Num 5, pp 938-943, issn 0018-9383Article

An analytic saturation model for drain and substrate currents of conventional and LDD MOSFET'sGWO-SHENG HUANG; CHING-YUAN WU.I.E.E.E. transactions on electron devices. 1990, Vol 37, Num 7, pp 1667-1677, issn 0018-9383, 11 p.Article

Monolithically integrated logic NOR gate based on GaAs/AlGaAs three-terminal junctionsMÜLLER, C. R; WORSCHECH, L; HÖPFNER, P et al.IEEE electron device letters. 2007, Vol 28, Num 10, pp 859-861, issn 0741-3106, 3 p.Article

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